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HD74LS164_15 Datasheet, PDF (4/11 Pages) Renesas Technology Corp – 8-Bit Parallel-Out Serial-in Shift Register
HD74LS164
Function Table
Inputs
Outputs
Clear
Clock
A
B
QA
QB……QH
L
X
X
X
L
L
L
H
L
X
X
QA0
QB0
QH0
H
↑
H
H
H
QAn
QGn
H
↑
L
X
L
QAn
QGn
H
↑
X
L
L
QAn
QGn
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. QA0, QB0, QH0; the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions
were established.
4. QAn, QGn; the level of QA or QG before the most-recent ↑ transition of the clock; indicates a one-bit shift.
Block Diagram
Clear
Clock
Serial A
Inputs B
Clear
R QA
Clear
R QB
Clear
R QC
Clear
R QD
Clear
R QE
Clear
R QF
Clear
R QG
Clear
R QH
CK
S QA
CK
S QB
CK
S QC
CK
S QD
CK
S QE
CK
S QF
CK
S QG
CK
S QH
Output Output Output Output Output Output Output Output
QA
QB
QC
QD
QE
QF
QG
QH
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN
7
Power dissipation
PT
400
Storage temperature
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Clock pulse width
Clear pulse width
Data setup time
Data hold time
Symbol
VCC
IOH
IOL
Topr
ƒclock
tw (CK)
tw (CLR)
tsu
th
Min
4.75
—
—
–20
0
20
20
15
5
Typ
5.00
—
—
25
—
—
—
—
—
Max
5.25
–400
8
75
25
—
—
—
—
Unit
V
V
mW
°C
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
Rev.2.00, Feb.18.2005, page 2 of 8