HD74HC77 Datasheet, PDF (4/7 Pages) Hitachi Semiconductor – 4-bit Bistable Latch

HD74HC77
Test Circuit
VCC
Input
Pulse generator
Zout = 50 Ω
Input
Pulse generator
Zout = 50 Ω
VCC
Enable _Q
Data Q
Output
Output
C_L = 50 pF
C_L = 50 pF
Note: C_L includes the probe and jig capacitance.
Waveforms
• Waveform − 1
t_r
t_w
t_f
t_w
90 %
90 %
D
50 %
50 %
V_CC
50 %
10 %
10 %
0V
t_su
t_h
t_su
t_h
t_r
t_f
Latch
90 % 90 %
V_CC
Enable
50 % 50 %
50 %
50 %
10 %
10 %
t_w
t_w
t_PHL
0V
t_PLH
t_PHL
t_PLH
90 %
90 %
Q
50 %
50 %
10 %
10 %
t_TLH
t_THL
V_OH
V_OL
Note: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t_f ≤ 6 ns
Rev.2.00, Oct 06, 2005 page 4 of 6