HD74AC164_15 Datasheet, PDF (4/11 Pages) Renesas Technology Corp – Serial-In, Parallel-Out Shift Register

HD74AC164/HD74ACT164
Logic Symbol
A
B
CP
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Pin Names
A, B
CP
MR
Q₀ to Q₇
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active Low)
Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each
of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an
active High Enable for data entry through the other inputs. An unused input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q₀ the logical
AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (MR)
input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
Mode Select Table
Inputs
Outputs
Operating Mode
MR
Reset (Clear)
L
A
X
B
X
Q₀
L
Q₁ to Q₇
L to L
Shift
H
L
L
L
q₀ to q₆
H
L
H
L
q₀ to q₆
H
H
L
L
q₀ to q₆
H
H
H
H
q₀ to q₆
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
q_n : Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High
clock transition.
Logic Diagram
A
B
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CD
CD
CD
CD
CD
CD
CD
CD
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 2 of 8