2SK3814_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

2SK3814
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
IDSS
IGSS
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
VDS = 60 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 30 A
VGS = 10 V, ID = 30 A
VGS = 4.5 V, ID = 30 A
Input Capacitance
Ciss
VDS = 10 V
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Coss
Crss
td(on)
VGS = 0 V
f = 1 MHz
VDD = 30 V, ID = 30 A
Rise Time
Turn-off Delay Time
tr
td(off)
VGS = 10 V
RG = 0 Ω
Fall Time
Total Gate Charge
tf
QG
VDD = 48 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
QGD
VF(S-D)
trr
Qrr
ID = 60 A
IF = 60 A, VGS = 0 V
IF = 60 A, VGS = 0 V
di/dt = 100 A/μs
MIN.
1.5
22
TYP.
2.0
44
7.0
7.9
5450
550
350
23
8.5
85
7.7
95
17
26
0.95
36
40
MAX.
10
±100
2.5
8.7
10.5
1.5
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D16740EJ2V0DS