2SK3484_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

2SK3484
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Gate Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(off)
| yfs |
RDS(on)1
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 8 A
VGS = 10 V, ID = 8 A
RDS(on)2 VGS = 4.5 V, ID = 8 A
Input Capacitance
Ciss
VDS = 10 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 50 V, ID = 8 A
Rise Time
tr
VGS = 10 V
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
tf
Total Gate Charge
QG
VDD = 80 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 16 A
IF = 16 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 16 A, VGS = 0 V
Qrr
di/dt = 100 A/ μs
Note Pulsed
MIN. TYP. MAX. UNIT
10 μA
±10 μA
1.5 2.0 2.5 V
4.7 9.5
S
100 125 mΩ
110 148 mΩ
900
pF
110
pF
50
pF
9.0
ns
5.0
ns
30
ns
4.0
ns
20
nC
3.0
nC
5.0
nC
1.0
V
60
ns
122
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
ID
VDD
IAS ^BVDSS
VDS
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VGS
90%
ID
90%
ID
Wave Form
0 ^10%
td(on)
ID
tr td(off)
90%
10%
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D15069EJ3V0DS