2SJ550 Datasheet, PDF (4/9 Pages) Hitachi Semiconductor – Silicon P Channel MOS FET High Speed Power Switching

2SJ550(L), 2SJ550(S)
Static Drain to Source on State Resistance
vs. Temperature
0.40
Pulse Test
0.32
0.24
–5 A
–10 A
I_D = –15 A
0.16 ^VGS ^{= –4 V}
0.08
0
–40
–10 V
–5 A, –10 A, –15 A
0
40 80 120 160
Case Temperature Tc (°C)
Body-Drain Diode Reverse
Recovery Time
500
200
100
50
20
10
5
–0.1 –0.2
di / dt = 50 A / µs
V_GS = 0, Ta = 25°C
–0.5 –1 –2 –5 –10 –20
Reverse Drain Current I_DR (A)
Dynamic Input Characteristics
0
0
V_DD = –10 V
–25 V
–20
–50 V
–4
–40
V_GS
V_DS
–60
V_DD = –50 V
–25 V
–10 V
–80
I_D = –15 A
–100
0
8
16 24 32
Gate Charge Qg (nc)
–8
–12
–16
–20
40
Forward Transfer Admittance vs.
Drain Current
100
30
Tc = –25°C
10
3
25°C
75°C
1
0.3
V_DS = –10 V
Pulse Test
0.1
–0.1 –0.3 –1 –3 –10 –30 –100
Drain Current I_D (A)
10000
Typical Capacitance vs.
Drain to Source Voltage
3000
1000
Ciss
300
Coss
100
Crss
30
V_GS = 0
f = 1 MHz
10
0 –10 –20 –30 –40 –50
Drain to Source Voltage V_DS (V)
1000
500
Switching Characteristics
V_GS = –10 V, V_DD = –30 V
PW = 5 µs, duty ≤ 1 %
200
td(off)
100
tf
50
tr
20
10
–0.1 –0.2 –0.5 –1 –2
td(on)
–5 –10 –20
Drain Current I_D (A)
Rev.3.00 Sep 07, 2005 page 4 of 8