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2SJ496_11 Datasheet, PDF (4/8 Pages) Renesas Technology Corp – Silicon P Channel MOS FET | |||
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2SJ496
Static Drain to Source on State Resistance
vs. Temperature
0.5
Pulse Test
0.4
â2 A
0.3
ID = â5 A
0.2
VGS = â4 V
â1 A
0.1
â10 V
â5 A
â1 A, â2 A
0
â40 0
40 80 120 160
Case Temperature Tc (°C)
Body-Drain Diode Reverse
Recovery Time
500
200
100
50
20
10
5
â0.1 â0.2
di / dt = 50 A / μs
VGS = 0, Ta = 25°C
â0.5 â1 â2 â5 â10
Reverse Drain Current IDR (A)
Dynamic Input Characteristics
0
0
VDD = â10 V
ID = â5 A
â25 V
â20
â50 V
â4
â40
VDS
VGS
â8
â60
â12
VDD = â50 V
â25 V
â80
â10 V
â16
â100
0
8
16 24 32
Gate Charge Qg (nc)
â20
40
Preliminary
Forward Transfer Admittance vs.
Drain Current
20
10
5
Tc = â25°C
25°C
2
75°C
1
0.5
0.2
â0.1 â0.2
â0.5 â1
VDS = â10 V
Pulse Test
â2 â5 â10
Drain Current ID (A)
2000
1000
500
Typical Capacitance vs.
Drain to Source Voltage
Ciss
200
Coss
100
50
Crss
20 VGS = 0
f = 1 MHz
10
0 â10 â20 â30 â40 â50
Drain to Source Voltage VDS (V)
1000
Switching Characteristics
300
td(off)
100
tf
30
tr
td(on)
10
3
1
â0.1 â0.2
VGS = â10 V, VDD = â30 V
PW = 5 μs, duty ⤠1 %
â0.5 â1 â2 â5 â10
Drain Current ID (A)
R07DS0433EJ0400 Rev.4.00
Jun 07, 2011
Page 4 of 7
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