PGA112 Datasheet, PDF (39/47 Pages) Texas Instruments – Single-Supply, Single-Ended, Precision Programmable Gain Amplifier with MUX

PGA112, PGA113
PGA116, PGA117
www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008
2. Signal trace routing. Keep V_OUT and other low
impedance traces away from MUX channel inputs
that are high impedance. Poor signal routing can
cause positive feedback, unwanted oscillations,
or excessive overshoot and ringing on
step-changing signals. If the input signals are
particularly noisy, separate MUX input channels
with guard traces on either side of the signal
traces. Connect the guard traces to ground near
the PGA and at the signal entry point into the
PCB. On multilayer PCBs, ensure that there are
no parallel traces near MUX input traces on
adjacent layers; capacitive coupling from other
layers can be a problem. Use ground planes to
isolate MUX input signal traces from signal traces
on other layers.
Additionally, group and route the digital signals
into the PGA as far away as possible from the
analog MUX input signals. Most digital signals
are fast rise/fall time signals with low-impedance
drive capability that can easily couple into the
high-impedance inputs of the input MUX
channels. This coupling can create unwanted
noise that gains up to V_OUT.
3. Input MUX channels and source impedance.
Input MUX channels are high-impedance; when
combined with high gain, the channels can pick
up unwanted noise. Keep the input signal
sources low-impedance (< 10kΩ). Also, consider
bypassing input MUX channels with a ceramic
bypass capacitor directly at the MUX input pin.
Bypass capacitors greater than 100pF are
recommended. Lower impedances and a bypass
capacitor placed directly at the input MUX
channels keep crosstalk between channels to a
minimum as a result of parasitic capacitive
coupling from adjacent PCB traces and pin-to-pin
capacitance.
APPLICATIONS: DRIVING/INTERFACING TO
ADCS
CDAC SAR ADCs contain an input sampling
capacitor, C_SH, to sample the input signal during a
sample period as shown in Figure 79. After the
sample period, C_SH is removed from the input signal.
Subsequent comparisons of the charge stored on C_SH
are performed during the ADC conversion process.
To achieve optimal op amp stability, input signal
settling, and the demands for charge from the input
signal conditioning circuitry, most ADC applications
are optimized by the use of a resistor (R_FILT) and
capacitor (C_FILT) filter placed between the op amp
output and ADC input. For the PGA112/PGA113, or
the PGA116/PGA117, setting C_FILT = 1nF and R_FILT =
100Ω yields optimum system performance for
sampling converters operating at speeds up to
500kHz, depending upon the application settling time
and accuracy requirements.
V_CAL/CH0
CH1
3
2
10kW
80kW
+5V
MUX
CAL1
0.9V_{CAL CAL2}
0.1V_{CAL CAL3}
CAL4
10kW
AV_DD
1
C_BYPASS
0.1mF
DV_DD
10
PGA112
PGA113
(MSOP-10)
Output
Stage
C_BYPASS
0.1mF
5 V_OUT
G=1
R_F
V_REF
CAL2/3
R_I
7 SCLK
SPI
Interface
8 DIO
9 CS
6
GND
4
V_REF
R_FILT
100W
C_FILT
(1nF)
12-Bit Settling ® 500kHz
16-Bit Settling ® 300kHz
+3V
C_BYPASS
0.1mF
C_SH
40pF
CDAC SAR
ADC
Figure 79. Driving/Interfacing to ADCs
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): PGA112 PGA113 PGA116 PGA117