H8S2319 Datasheet, PDF (383/1144 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.4 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 9.5 shows the register combinations used in buffer operation.
Table 9.5 Register Combinations in Buffer Operation
Channel
0
3
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9.16.
Compare match signal
Buffer register
Timer general
register
Comparator
Figure 9.16 Compare Match Buffer Operation
TCNT
Rev.7.00 Feb. 14, 2007 page 351 of 1108
REJ09B0089-0700