H8S2111B Datasheet, PDF (383/582 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 14 Keyboard Buffer Controller
This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is
provided with functions conforming to the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line
(KCLK), providing economical use of connectors, board surface area, etc. Figure 14.1 shows a
block diagram of the keyboard buffer controller.
14.1 Features
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
KD
(PS2AD,
PS2BD,
PS2CD)
KCLK
(PS2AC,
PS2BC,
PS2CC)
KDI
Control
logic
KCLKI
Parity
KDO
KCLKO
KBBR
KBCRH
KBCRL
Internal
data bus
Register counter value
KBI interrupt
[Legend]
KD:
KCLK:
KBBR:
KBCRH:
KBCRL:
KBC data I/O pin
KBC clock I/O pin
Keyboard data buffer register
Keyboard control register H
Keyboard control register L
Figure 14.1 Block Diagram of Keyboard Buffer Controller
IFKEY10A_000020020700
Rev. 1.00, 05/04, page 349 of 544