M37274EFSP Datasheet, PDF (38/148 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
DATA SLICER
The M37274EFSP includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a
composite video signal. A composite video signal which makes the
sync chip’s polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit can
be cut off by setting bit 0 of data slicer control register 1 (address
00EA16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB16)
to “0.” These settings can realize the low-power dissipation.
Composite
video
signal
0.1 µF _470Ω
Hundred of kiloohms
to 1 MΩ
560 pF _{1 µF}
1 kΩ
200 pF
15 kΩ
Sync pulse counter
register
(address 020F16)
CVIN
HSYNC
HLF RVCO
Synchronizing
signal counter
Clock run-in register 2
(address 00E716)
100111 1
Clamping
circuit
Low-pass
filter
Sync slice
circuit
VHOLD
1000 pF
Reference
voltage
generating
circuit
+
–
Comparator
Data slicer control
register 3
(address 021016)
Clock run-in detect
register 3
(address 020816)
Clock run-in
register 3
(address 020916)
Synchronizing
separation
circuit
Timing signal
generating
circuit
Clock run-in
determination
circuit
Data slice line
specification
circuit
Start bit detecting
circuit
Data clock
generating circuit
Data slicer control register 2
(address 00EB16)
0 00
Data slicer control register 1
(address 00EA16)
0 00
Data slicer ON/OFF
Window register
(address 00E216)
00
0101
Clock run-in register 1
(address 00E616)
100
Caption position register
(address 00E016)
Start bit position register
(address 00E116)
External circuit
Note: Make the length of wiring which is
connected to VHOLD, HLF, RVCO
and CVIN pin as short as possible
so that a leakage current may
not be generated when mounting
a resistor or a capacitor on each
pin.
Data register 2
(address 00E516)
Sync slice register 3
(address 00E316)
0000101
16-bit shift register
Clock run-in detect register 1
(address 00E816)
high-order
Data register 4
(address 00ED16)
low-order
Clock run-in detect register 2
(address 00E916)
Data register 1
(address 00E416) _{Interrupt request}
generating circuit
Data slicer
interrupt
request
Data register 3
(address 00EC16)
Data bus
Fig. 31. Data Slicer Block Diagram
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