M3882 Datasheet, PDF (37/62 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3882 Group
LPCSR write signal
LPCSR bit
(LPC interface software reset signal)
1.5 cycle of φ
CPU Data bus bit 2
LPCSR write signal
CPU RESET
DQ
CK
R
φ
CPU RESET
DQ
CK
R
LRESET
DQ
CK
R
LPC interface reset signal
Fig. 30 Reset timing and block
Table 10 Reset conditions of LPC interface function
Pin name / Internal register
LRESET = “L”
Note
P80/LAD0
P81/LAD1
P82/LAD2
P83/LAD3
P84/LFRAME
P85/LRESET
P86/LCLK
Input data bus buffer registeri
Output data bus buffer registeri
Uxi flag 7, 6, 5, 4, 2
Tri-state
Input
LPC bus interface function
Input
Keep same value before
LRESET goes “L”.
XA2i flag
IBFi flag
OBFi flag
LPCi address register
LPCCON
Initialization to “0”.
Initialization to “0”.
Initialization to “0”.
Keep same value before
LRESET goes “L”.
There is possibility to generate
IBF interrupt request.
There is possibility to generate
OBE interrupt request.
Rev.1.01 Nov 14, 2005 page 37 of 60
REJ03B0089-0101