R8C2K Datasheet, PDF (346/471 Pages) Renesas Technology Corp – MCU

R8C/2K Group, R8C/2L Group
17. Serial Interface
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1 1
register
0
TI bit in UiC1 1
register
0
TXDi
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2
D3 D4 D5
D6 D7
Stop pulsing
because the TE bit is set to 0
P SP
ST D0 D1
TXEPT bit in 1
UiC0 register 0
IR bit SiTIC
1
register
0
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
• PRYE bit in UiMR register = 1 (parity enabled)
fj: Frequency of UiBRG count source (f1, f8, f32)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 2
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1 1
register
0
TI bit in UiC1 1
register
0
TXDi
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Start
bit
Stop Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
TXEPT bit in 1
UiC0 register ₀
IR bit in SiTIC 1
register
0
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 2
Figure 17.10 Transmit Timing in UART Mode
Rev.1.10 Dec 21, 2007 Page 329 of 450
REJ09B0406-0110