3800 Datasheet, PDF (34/174 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES

Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Fig. 13 Interrupt control
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request
b7
b0 _{Interrupt edge selection register}
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
INT5 active edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0 _{Interrupt request register 1}
b7
b0 _{Interrupt request register 2}
(IREQ1 : address 003C16)
(IREQ2 : address 003D16)
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
INT4 interrupt request bit
INT5 interrupt request bit
Not used (return “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
b0 _{Interrupt control register 2}
(ICON2 : address 003F16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
INT4 interrupt enable bit
INT5 interrupt enable bit
Not used (return “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
3800 GROUP USER’S MANUAL
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