H83724 Datasheet, PDF (332/352 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series

C.3 Port 3 Block Diagram
STBY
V_CC
Decoder
P3_n
Option
SGDL
PDR3
(bit n)
V_disp
PDR3: Port data register 3
n = 0 to 3
SGDL: Segment data latch
LTCLK: Segment data latch clock
SR₄ to SR₀: VFD segment control register bits 4 to 0
VFLAG: VFD segment control register bit 7
Figure C-3 Port 3 Block Diagram
VFD controller/
driver
SR₄ to SR₀
VFLAG
LTCLK
RAM
DATA
Internal
data bus
Rev. 3.00, 12/94, page 317 of 334