H83834U Datasheet, PDF (331/497 Pages) Renesas Technology Corp – Single-Chip Microcomputer

3. Break detection and processing
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the
parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER
bit is cleared to 0 it will be set to 1 again.
4. Sending a mark or break signal
When TE is cleared to 0 the TXD pin becomes an I/O port, the level and direction (input or
output) of which are determined by the PDR and PCR bits. This feature can be used to place the
TXD pin in the mark state or send a break signal.
To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and
PCR bits both to 1. Since TE is cleared to 0, TXD becomes a general output port outputting the
value 1.
To send a break signal during data transmission, set the PCR bit to 1 and clear the PDR bit to 0,
then clear TE to 0. When TE is cleared to 0 the transmitter is initialized, regardless of its current
state, so the TXD pin becomes an output port outputting the value 0.
5. Receive error flags and transmit operation (sysnchronous mode only)
When a receive error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if
TDRE is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note
that clearing RE to 0 does not clear the receive error flags.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode SCI3 operates on a base clock with 16 times the bit rate frequency. In
receiving, SCI3 synchronizes internally with the falling edge of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See
figure 10-4-21.
318