R1QBA7236ABB Datasheet, PDF (33/39 Pages) Renesas Technology Corp – 72-Mbit DDRII+ SRAM 2-word Burst

R1QBA72 / R1QEA72 Series
Boundary Scan Order
Bit # Ball ID
71 3C
72 1D
73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1H
85 1J
86 2J
87 3K
88 3J
Signal names
x9
x18
x36
NC
NC
DQ28
NC
NC
NC
NC
NC
NC
DQ5
DQ11
DQ20
NC
NC
DQ29
NC
NC
NC
NC
NC
NC
NC
DQ12
DQ30
NC
NC
DQ21
NC
NC
NC
NC
NC
NC
DQ6
DQ13
DQ22
NC
NC
DQ31
/DOFF /DOFF /DOFF
NC
NC
NC
NC
NC
NC
NC
DQ14
DQ23
NC
NC
DQ32
89 2K
NC
NC
NC
90 1K
NC
NC
NC
Bit # Ball ID
91 2L
92 3L
93 1M
94 1L
95 3N
96 3M
97 1N
98 2M
99 3P
100 2N
101 2P
102 1P
103 3R
104 4R
105 4P
106 5P
107 5N
108 5R
109 ⎯
⎯⎯
Signal names
x9
x18
x36
DQ7
DQ15 DQ33
NC
NC
DQ24
NC
NC
NC
NC
NC
NC
NC
DQ16 DQ25
NC
NC
DQ34
NC
NC
NC
NC
NC
NC
DQ8
DQ17 DQ26
NC
NC
DQ35
NC
NC
NC
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
INTER- INTER- INTER-
NAL
NAL
NAL
⎯
⎯
⎯
Notes:
In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K
(except EXTEST, SAMPLE-Z).
Rev. 0.11 : 2013.01.15
R10DS0170EJ0011
PAGE:33