M37151M6_02 Datasheet, PDF (30/138 Pages) Renesas Technology Corp – SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
8.6.1 I²C Data Shift Register
The I²C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I²C data shift register is in a write enable status only when the
ESO bit of the I²C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I²C data shift register.
When both the ESO bit and the MST bit of the I²C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I²C data shift register. Reading data from the I²C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I²C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
I²C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register 1(S0) [Address 00F616]
B Name
Functions
0 D0 to D7 This is an 8-bit shift register to store
to
receive data and write transmit data.
7
After reset R W
Indeterminate R W
Note : To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 I²C Data Shift Register
Rev.1.00 Nov 01, 2002 page 30 of 136
REJ03B0129-0100Z