M64893AGP Datasheet, PDF (3/12 Pages) Renesas Technology Corp – SERIAL INPUT PLL FREQUENCY SYNTHES IZER FOR TV/VCR

M64893AGP
Method of Setting Data
The programmable divider uses 15bits Setting up the band switching output uses 4bits.
The test mode data use s 8bits. The total bits used is 27bits. Data is read in when the enable signal is “H” and the clock
signal falls.
The band switching data is read in the 4th pulse of the clock signal. The programmable driver data is read into the fall
of the 19th pulse of the clock signal .When the enable signal goes to “L” Before the 19th pulse of the enable signal,
only the band switching data is updated and other data is ignored.
ENA
DATA
CLK
BS4 _{BS3 BS2} BS1 29 28 ₂₇ 26 25 24 23 22 21 ²⁰ 24 23 22 21 ²⁰
M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
BAND
SWITCHING
DATA
MAIN COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
SWALLOW COUNTER
DIVISION RATIO SETTING
READ INTO LATCH
How to Set The Dividing Radio of The Programmable Divider
Total division N is given by the following from formulas in addition to the prescaler used the previous stage.
N = 8*(32 M+S) M: 10 bit main counter division
S: 5 bit swallow counter division
The M and S counters are binary the possible ranges of division are follows.
32 ≤ M ≤ 1023
0 ≤ S ≤ 31
Therefore, the rage of division N is 8,192 to 262, 136.
The tuning frequency fvco is given in the following equations.
fvco = fref*N
= 6.25*8*(32M+S)
= 50.0*8*(32M+S) [KHz]
Therefore, the tuning frequency range is from 51.2 MHz to 1000 MHz
Rev.1.00, Jul.25.2003, page 3 of 11