M62384FP_08 Datasheet, PDF (3/8 Pages) Renesas Technology Corp – 8-Bit, 4-Channel, 3 to 5 V D-A Converter (Buffered)

M62384FP
Absolute Maximum Ratings
Item
Power supply voltage
Digital input voltage
Reference voltage input voltage
D-A output voltage
Permissible loss
Operating ambient temperature
Storage temperature
Symbol
VCC,VDD
VDIN
Vref
VAO
Pd
Topr
Tstg
Rated Value
–0.3 to 7.0
–0.3 to Vcc+0.3 (≤ 7.0)
–0.3 to Vcc+0.3 (≤ 7.0)
–0.3 to Vcc+0.3 (≤ 7.0)
300
–20 to +75
–40 to +125
(Unless specified otherwise, Ta = 25ºC)
Unit
Conditions
V
V DC voltage (“H” level)
V
V
mW
°C
°C
Recommended Operating Conditions
(Unless specified otherwise, VCC = VDD = 5 V ±10%, Vref = 2 V to VCC, VSS = GND = 0 V, fsck = 5 MHz,
VDINH = VDD, VDINL = VSS, Ta = 20ºC to 75ºC)
Specification Values
Item
Symbol Min.
Typ.
Max.
Unit
Test Conditions
Analog power supply voltage
VCC
2.7
5.5
V
VCC = VDD
Digital power supply voltage
VDD
2.7
5.5
V
VCC = VDD
Reference voltage
Vref
2.0
5.5
V
Vref ≤ VCC
Serial clock frequency
fsck
10
MHz
“H” level digital input voltage
VDINH 0.5VDD
VDD
V
“L” level digital input voltage
VDINL
VSS
0.2VDD
V
Clock “H” pulse width
tsckH
30
ns VCC = VDD ≥ 2.7V
Clock “L” pulse width
tsckL
30
ns VCC = VDD ≥ 2.7V
Clock rise time
tsckR
200
ns
Clock fall time
tsckF
200
ns
Data setup time
tDCH
10
ns
Data hold time
tCHD
20
ns
Load setup time
tCHL
40
ns
Load hold time
tLDC
20
ns
Load “H” pulse width
tLDH
20
ns
Reset “L” pulse width
tRSTL
50
ns
Load setup time after reset release tRCHL
50
ns
Timing Chart
SCK
SDI
SLD
RST
t SCKR
t SCKH
t SCKF
t SCKL
t DCH
t RSTL
t CHD
t CHL
t RCHL
t LDH
t LDC
t LDD
AO
REJ03F0077-0200 Rev.2.00 Mar 25, 2008
Page 3 of 7