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HD74LV273A_15 Datasheet, PDF (3/12 Pages) Renesas Technology Corp – Octal D-type Flip-Flops with Clear | |||
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HD74LV273A
Octal D-type Flip-Flops with Clear
REJ03D0330â0300Z
(Previous ADE-205-273A (Z))
Rev.3.00
Jun. 25, 2004
Description
The HD74LV273A has eight edges trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having
the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The
clear input when low sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-
powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
⢠VCC = 2.0 V to 5.5 V operation
⢠All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
⢠All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
⢠Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
⢠Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
⢠Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
HD74LV273AFPEL
SOPâ20 pin (JEITA) FPâ20DAV
FP
HD74LV273ARPEL
SOPâ20 pin (JEDEC) FPâ20DBV
RP
HD74LV273ATELL
TSSOPâ20 pin
TTPâ20DAV
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
CLR
CLK
D
Output Q
L
X
X
L
H
â
H
H
H
â
L
L
H
â
X
Q0
Note: H: High level
L: Low level
X: Immaterial
â: Low to high transition
â: High to low transition
Q0: Output level before the indicated steady state input conditions were established.
Rev.3.00 Jun. 25, 2004 page 1 of 9
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