HD74LV1GW97A Datasheet, PDF (3/9 Pages) Renesas Technology Corp – Configurable Multiple-Function Gate

HD74LV1GW97A
Function Selection Table
Logic Function
2 to 1 data Selector
2–inputs AND
2–inputs OR with one input inverted
2–inputs NAND with one input inverted
2–inputs AND with one input inverted
2–inputs NOR with one input inverted
2–inputs OR
Inverter
Non–Inverter Buffer
Logic Configurations
V_CC
A
1 (IN1) (IN2) 6
A/B
A/B
A
B
Y
2 (GND) (V_CC) 5
B
3 (IN0)
(Y) 4
Y
Figure 1. 2 to 1 Data Selecter
V_CC
A
B
1 (IN1) (IN2) 6
A
A
Y
B
A
B
2 (GND) (V_CC) 5
A
Y
B
B
3 (IN0)
(Y) 4
Y
Figure 2. 2–inputs AND Gate
V_CC
A
B
B
1 (IN1) (IN2) 6
A
A
Y
B
A
B
2 (GND) (V_CC) 5
A
Y
3 (IN0)
(Y) 4
Y
B
Figure 4. 2–inputs AND Gate
with A input inverted
V_CC
1 (IN1) (IN2) 6
A
A
Y
2 (GND) (V_CC) 5
A
3 (IN0)
(Y) 4
Y
Figure 6. Inverter
Rev.3.00, May 19, 2006 page 3 of 8
Figure No.
1
2
3
3
4
4
5
6
7
V_CC
1 (IN1) (IN2) 6
A
Y
2 (GND) (V_CC) 5
Y
B
3 (IN0) (Y) 4
Y
Figure 3. 2–inputs OR Gate
with A input inverted
V_CC
B
1 (IN1) (IN2) 6
A
Y
2 (GND) (V_CC) 5
Y
3 (IN0)
(Y) 4
Y
Figure 5. 2–inputs OR Gate
V_CC
A
1 (IN1) (IN2) 6
Y
2 (GND) (V_CC) 5
3 (IN0) (Y) 4
Y
Figure 7. Non–Invert Butter