HD74AC195 Datasheet, PDF (3/8 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register

HD74AC195
Pin Names
CP
D₀ to D₃
PE
MR
J, K
Q₀ to Q₃, Q₃
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input
Asynchronous Master Reset
J-K or D Type Serial Inputs
Outputs
Timing Diagram
CP
MR
J
K
PE
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Clear
H
L
H
L
Serial Shift
Load
Serial Shift
Mode Select-Function Table
Inputs
Outputs
Operating Modes
Asynchronous Reset
MR CP PE J
K
D_n
Q₀
L
X
X
X
X
X
L
Q₁
L
Q₂
L
Q₃
L
Q₃
H
Shift, Set First Stage
H
Shift, Reset First Stage H
Shift, Toggle First Stage H
Shift, Retain First Stage H
Parallel Load
H
H : HIGH Voltage Level
HHHXH
q₀
q₁
q₂
q₂
H
L
L
X
L
q₀
q₁
q₂
q₂
H
H
L
X
q₀
q₀
q₁
q₂
q₂
H
L
H
X
q₀
q₀
q₁
q₂
q₂
L
X
X
d_n
d₀
d₁
d₂
d₃
d₃
L : LOW Voltage Level
X : Immaterial
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH
transition.
: LOW-to-HIGH clock transition.
Rev.2.00, Jul.16.2004, page 3 of 7