HD74AC182 Datasheet, PDF (3/7 Pages) Hitachi Semiconductor – Carry Lookhead Generator

HD74AC182
C_{n + x} = G₀ + P₀C_n
C_{n + y} = G₁ + P₁G₀ + P₁P₀C_n
C_{n + z} = G₂ + P₂G₁ + P₂P₁G₀ + P₂P₁P₀C_n
G = G₃ + P₃G₂ + P₃P₂G₁ + P₃P₂P₁G₀
P = P₃P₂P₁P₀
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand
mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.
Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by
dropping the last HD74AC182/HD74ACT182.
Truth Table
C_n
X
L
X
H
X
X
L
X
X
H
X
X
X
L
X
X
X
H
H:
L:
X:
G₀
P₀
G₁
H
H
H
X
L
X
X
L
X
X
H
H
H
H
H
X
H
X
X
L
L
X
X
X
L
X
X
X
X
X
X
H
H
H
H
H
X
H
X
X
X
X
X
L
L
X
X
X
L
X
X
X
X
X
X
H
H
H
X
X
X
X
X
L
L
X
H
X
X
X
L
High Voltage Level
Low Voltage Level
Immaterial
Inputs
P₁
G₂
H
X
X
X
L
L
X
H
H
H
X
H
X
H
X
L
X
X
L
X
L
X
X
X
X
H
H
H
X
H
X
X
X
L
X
X
L
X
X
H
X
X
L
P₂
H
X
X
X
X
L
L
L
X
H
X
X
X
X
L
L
X
X
H
X
L
G₃
H
H
H
H
L
X
X
X
P₃
H
X
X
X
X
L
L
L
X
X
X
H
L
C_{n + x}
L
L
H
H
C_{n + y}
L
L
L
H
H
H
Outputs
C_{n + z}
G
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
P
H
H
H
H
L
Rev.2.00, Jul.16.2004, page 3 of 6