H83814 Datasheet, PDF (274/456 Pages) Renesas Technology Corp – single-chip microcomputers

Transmitting
processor
Receiving
processor A
(ID = 01)
Communication line
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial data
H'01
(MPB = 1)
ID-sending cycle
(receiving processor
address)
MPB: Multiprocessor bit
H'AA
(MPB = 0)
Data-sending cycle
(data sent to receiving
processor designated
by ID)
Figure 10-3-16 Example of Interprocessor Communication Using Multiprocessor Format
(Data H'AA Sent to Receiving Processor A)
Four communication formats are available. Parity-bit settings are ignored when a multiprocessor
format is selected. For details see table 10-3-11.
For a description of the clock used in multiprocessor communication, see 10.3.4, Operation in
Asynchronous Mode.
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