R8C-24_1 Datasheet, PDF (270/525 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits⁽¹⁾
After Reset
10000000b
Function
RW
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM3 mode.
RW
CMD1
RW
Normal-phase output level select bit This bit is disabled in PWM3 mode.
(enabled in reset synchronous PWM
OLS0 _{mode or complementary PWM mode)}
RW
Counter-phase output level select bit This bit is disabled in PWM3 mode.
(enabled in reset synchronous PWM
OLS1 _{mode or complementary PWM mode)}
RW
A/D trigger enable bit
This bit is disabled in PWM3 mode.
ADTRG ^{(enabled in complementary PWM mode)}
RW
A/D trigger edge select bit
This bit is disabled in PWM3 mode.
ADEG ^{(enabled in complementary PWM mode)}
RW
External clock input select bit
STCLK
Set this bit to 0 (external clock input
disabled) in PWM3 mode.
RW
PWM3 mode select bit⁽²⁾
PWM3
Set this bit to 0 (PWM3 mode) in PWM3
mode.
RW
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.99 TRDFCR Register in PWM3 Mode
Rev.3.00 Feb 29, 2008 Page 253 of 485
REJ09B0244-0300