RMQSAA3636DGBA_15 Datasheet, PDF (27/30 Pages) Renesas Technology Corp – 36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency)

RMQSAA3636DGBA, RMQSAA3618DGBA
ID Register
Preliminary Datasheet
Revision
number
Type number
(31:28)
(27:12)
#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
RMQSAA3636DGBA 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0
Start bit (0)
Vendor JEDEC code
(11:1)
876543
001000
→→
↓
↓
210
111
RMQSAA3618DGBA 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1
TAP Controller State Diagram
1
Test Logic Reset
0
1
Run Test/Idle
0
1
Select DR Scan
0
1
Capture DR
0
0
Shift DR
1
1
Exit1 DR
0
0
Pause DR
1
0
Exit2 DR
1
Update DR
10
1
Select IR Scan
0
1
Capture IR
0
0
Shift IR
1
1
Exit1 IR
0
0
Pause IR
1
0
Exit2 IR
1
Update IR
10
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
R10DS0242EJ0002 Rev.0.02
Dec. 01, 2014
Page 27 of 29