H8S2116 Datasheet, PDF (26/842 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Figure 5.8 State Transition in Interrupt Control Mode 1 ............................................................ 108
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 .... 110
Figure 5.10 Interrupt Exception Handling.................................................................................. 111
Figure 5.11 Block Diagram of Address Break Function ............................................................ 113
Figure 5.12 Examples of Address Break Timing........................................................................ 115
Figure 5.13 Conflict between Interrupt Generation and Disabling............................................. 116
Section 7 I/O Ports
Figure 7.1 Noise Cancel Circuit ................................................................................................. 142
Figure 7.2 Noise Cancel Operation ............................................................................................ 142
Section 8 8-Bit PWM Timer (PWM)
Figure 8.1 Block Diagram of PWM Timer................................................................................. 198
Figure 8.2 Duty Cycle of the Output Waveform in Single-Pulse Mode ..................................... 205
Figure 8.3 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 207
Figure 8.4 Example of PWM Setting.......................................................................................... 208
Figure 8.5 Example Circuit when Using PWM as D/A.............................................................. 208
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1 PWMX (D/A) Block Diagram .................................................................................. 211
Figure 9.2 DACNT Access Operation (1) [CPU → DACNT (H'AA57) Writing] ..................... 219
Figure 9.2 DACNT Access Operation (2) [DACNT → CPU (H'AA57) Reading] .................... 220
Figure 9.3 PWMX (D/A) Operation ........................................................................................... 221
Figure 9.4 Output Waveform (OS = 0, DADR corresponds to T_L) ............................................ 224
Figure 9.5 Output Waveform (OS = 1, DADR corresponds to T_H) ............................................ 225
Figure 9.6 D/A Data Register Configuration when CFS = 1 ...................................................... 225
Figure 9.7 Output Waveform when DADR = H'0207 (OS = 1) ................................................. 226
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU............................................................................................ 230
Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 257
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 258
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] ............. 258
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] ....... 258
Figure 10.6 Example of Counter Operation Setting Procedure .................................................. 259
Figure 10.7 Free-Running Counter Operation ............................................................................ 260
Figure 10.8 Periodic Counter Operation..................................................................................... 261
Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 261
Figure 10.10 Example of 0 Output/1 Output Operation ............................................................. 262
Figure 10.11 Example of Toggle Output Operation ................................................................... 262
Figure 10.12 Example of Input Capture Operation Setting Procedure ....................................... 263
Figure 10.13 Example of Input Capture Operation .................................................................... 264
Rev. 1.00 Mar. 02, 2006 Page xxvi of xl