R8C54E_15 Datasheet, PDF (25/81 Pages) Renesas Technology Corp – RENESAS MCU

R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I
flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware
interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is
executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has
higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
The write value must be 0. The read value is undefined.
R01DS0043EJ0200 Rev.2.00
Sep 05, 2012
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