V850E2FK4-H_15 Datasheet, PDF (24/80 Pages) Renesas Technology Corp – 32-bit Single-Chip Microcontroller

Chapter 3
3.5.4 Condition 3
RESET is not used; WAKE/PWGD is used
Normal operating mode
Power supply specification
Parameter
REG0VDD, REG1VDD, IOVDD (rise) to
WAKE (rise) output delay time
WAKE (rise) to CVDD (rise)
CVDD (rise) to PWGD (rise)
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
FLMD0,1 (≤VIL) to REG0VDD, IOVDD
(fall)
WAKE (fall) to CVDD (0V)
Symbol
tR0WRD
tWCON
tCPWDH
tR0MDH
tMDR0OF
tWCOF
Condition
Ratings
Unit
Min Typ Max
-
-
2
ms
0
-
8
ms
0
-
-
ms
2
-
-
ms
0
-
-
ms
0
-
8
ms
REG0VDD
REG1VDD
IOVDD
CVDD
PWGD
FLMD0
P0_1/FLMD1
WAKE
3.0V
3.0V
1.1V
tWCON
tWCOF
VIL
tCPWDH
VIL
tROMDH
VIH
tR0WRD
VIL
tMDR0OF
VIL
The WAKE signal falls at the same time as the fall of the IOVDD voltage due to
the lack of output voltage.
Even if REG0VDD keeps some voltage, the WAKE signal falls at least 2ms
after the POC detection.
R01DS0143ED0100
24
Electrical Target Specification