R1QAA3636CBG Datasheet, PDF (24/38 Pages) Renesas Technology Corp – 36-Mbit QDRII+ SRAM 4-word Burst

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R1QAA36**CB* / R1QDA36**CB* Series
Parameter
Symbol
-19
-20
-22
-25
-27
-30
Unit Notes
Min Max Min Max Min Max Min Max Min Max Min Max
Setup Times
t_AVKH

Address valid to
K rising edge
(QDRII+ B2)
t_AVKH
ns 1, 8
0.30  0.33  0.40  0.40  0.40  0.40 
(QDRII+ B4 & DDRII+)
Control inputs
valid to
t_IVKH
(QDRII+ B2)

ns 1, 8
K rising edge
t_IVKH
0.30  0.33  0.40  0.40  0.40  0.40 
(QDRII+ B4 & DDRII+)
Data-in valid to
K, /K rising edge
t_DVKH
0.20  0.22  0.25  0.28  0.28  0.28  ns 1, 9
Hold Times
t_KHAX

K rising edge
to address hold
(QDRII+ B2)
t_KHAX
ns 1, 8
0.30  0.33  0.40  0.40  0.40  0.40 
(QDRII+ B4 & DDRII+)
K rising edge
to control inputs
t_KHIX
(QDRII+ B2)

ns 1, 8
hold
t_KHIX
0.30  0.33  0.40  0.40  0.40  0.40 
(QDRII+ B4 & DDRII+)
K, /K rising edge
to data-in hold
t_KHDX
0.20  0.22  0.25  0.28  0.28  0.28  ns 1, 9
Notes:
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and
hold times for all latching clock edges.
2. V_DD and V_DDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock
time begins once V_DD , V_DDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
This specification meets the QDR common spec. of 20 us.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a r0.1 ns variation from
echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured r100 mV from steady-state voltage.
6. At any given voltage and temperature t_CHQZ is less than t_CHQX1 and t_CHQV.
7. These parameters are sampled.
8. t_AVKH, t_IVKH, t_KHAX, t_KHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name). The following is the spec for the actual frequency.
0.30 ns for ื533MHz & >500MHz
0.33 ns for ื500MHz & >450MHz
0.40 ns for ื450MHz & ุ250MHz
9. t_DVKH, t_KHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for ื533MHz & >500MHz
0.22 ns for ื500MHz & >450MHz
0.25 ns for ื450MHz & >400MHz
0.28 ns for ื400MHz & ุ250MHz
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than t_KHKL (min).
3. V_DDQ is +1.5 V DC. V_REF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
Rev. 0.09a : 2011.09.14
R10DS0158EJ0009
PAGE : 24