7470 Datasheet, PDF (24/47 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The 7470/7471 group are reset according to the sequence shown
in Figure 15. It starts the program from the address formed by us-
ing the content of address FFFF16 as the high order address and
the content of the address FFFE16 as the low order address, when
the RESET pin is held at “L” level for no less than 2 µs while the
power voltage is in the recommended operating condition and
then returned to “H” level.
The internal initializations following reset are shown in Figure 16.
Example of reset circuit is Figure 14. Immediately after reset, timer
3 and timer 4 are connected, and counts the f(XIN) divided by 16.
At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The
reset is cleared when timer 4 overflows.
7470/7471 group
RESET
VCC
Fig. 14 Example of reset circuit
Address
(1) Port P0 direction register
(C116) …
0016
(2) Port P1 direction register
(C316) …
0016
(3) Port P2 direction register
(C516) …
0016
(4) Port P4 direction register
(C916) …
0 000
(5) P0 pull-up control register
(D016) …
0016
(6) P1–P5 pull-up control register (Note 1)(D116) …
0
00 000
(7) Edge selection register (EG) (D416) …
00 0 000
(8) A-D control register
(D916) … 0
01 000
(9) Serial I/O mode register (SM) (DC16) …
0016
(10) Timer 12 mode register (T12M) (F816) …
0016
(11) Timer 34 mode register (T34M) (F916) …
0016
(12) Timer mode register 2 (TM2) (FA16) … 0 0
00
(13) CPU mode register
(CM) (FB16) … 0 0 0 0 0 0 0
(14) Interrupt request register 1
(FC16) … 0 0
0 000
(15) Interrupt request register 2
(FD16) …
000
(16) Interrupt control register 1
(FE16) … 0 0
0 000
(17) Interrupt control register 2
(18) Program counter
(19) Processor status register
(FF16) …
(PCH) …
(PCL) …
(PS) …
000
Contents of address
FFFF16
Contents of address
FFFE16
1
Notes 1 : This address is allocated P1–P4 pull-up control register for
7470 group. Bit 6 is not used.
2 : Since the contents of both registers other than those listed
above (including timers and the serial I/O register) are
undefined at reset, it is necessary to set initial values.
Fig. 16 Internal state of microcomputer at reset
XIN
φ
RESET
Internal
RESET
SYNC
Address
Data
?
?
00, S 00, S-1 00, S-2 FFFE FFFF ADH,ADL
?
?
PCH
PCL
PS
ADL
ADH
Reset address
from the vector table
32768 counts of f(XIN)
Notes 1 : Frequency relation of XIN and φ is f(XIN)=2·φ.
2 : The mark “?” means that the address is changeable
depending upon the previous state.
Fig. 15 Timing diagram at reset
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