R1QLA4436RBG_15 Datasheet, PDF (22/31 Pages) Renesas Technology Corp – 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT

R1QLA4436RBG, R1QLA4418RBG
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Datasheet
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to V_SS to preclude middle level inputs.
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O Pin assignments
Description
Notes
TCK
Test clock input. All inputs are captured on the rising edge of TCK
2R
and all outputs propagate from the falling edge of TCK.
TMS
Test mode select. This is the command input for the TAP controller
10R
state machine.
Test data input. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is
TDI
11R
determined by the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction.
TDO
Test data output. Output changes in response to the falling edge of
1R
TCK. This is the output side of the serial registers placed between
TDI and TDO.
Notes:
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(T_A = -40 to +85°C , V_DD = 1.8V ±0.1V)
Parameter
Symbol
Min
Typ
Max Unit
Notes
Input high voltage
Input low voltage
Input leakage current
Output leakage current
Output low voltage
Output high voltage
Notes:
V_IH
V_IL
I_LI
I_LO
V_OL1
V_OL2
V_OH1
V_OH2
+1.3
-0.3
-5.0
-5.0
-
-
1.6
1.4
-
V_DD + 0.3 V
-
+0.5
V
-
+5.0
μA
0 V ≤ V_IN ≤ V_DD
-
+5.0
μA
0 V ≤ V_IN ≤ V_DD,
output disabled
-
0.2
V
I_OLC = 100 μA
-
0.4
V
I_OLT = 2 mA
-
-
V
|I_OHC| = 100 μA
-
-
V
|I_OHT| = 2 mA
1. All voltages referenced to V_SS (GND).
2. At power-up, V_DD and V_DDQ are assumed to be a linear ramp from 0V to V_DD(min.) or V_DDQ(min.) within
200ms. During this time, V_DDQ < V_DD and V_IH < V_DDQ.
During normal operation, V_DDQ must not exceed V_DD.
R10DS0144EJ0200 Rev.2.00
Aug 01, 2014
Page 22 of 30