RJK5030DPD_15 Datasheet, PDF (2/6 Pages) Renesas Technology Corp – Silicon N Channel MOS FET High Speed Power Switching

RJK5030DPD
Electrical Characteristics
Item
Drain to source breakdown voltage
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Static drain to source on state resistance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body-drain diode forward voltage
Body-drain diode reverse recovery time
Note: 4. Pulse test
Preliminary
(Ta = 25C)
Symbol Min Typ Max Unit
Test Conditions
V _{(BR) DSS} 500
—
—
V I_D = 1 mA, V_GS = 0
I_DSS
—
—
10
A V_DS = 500 V, V_GS = 0
I_GSS
—
—
0.1 A V_GS = 30 V, V_DS = 0
V_{GS (off)}
3.5
—
4.5
V V_DS = 10 V, I_D = 1 mA
R_{DS (on)}
—
1.3
1.6
 I_D = 2 A, V_GS = 10 V ^{Note 4}
Ciss
— 550
—
pF V_DS = 25 V
Coss
—
60
—
pF VGS = 0
Crss
—
10
—
pF ^{f = 1 MHz}
t_{d (on)}
t_r
t_{d (off)}
t_f
V_DF
t_rr
—
15
—
ns V_DD = 200 V
—
20
—
ns ID = 2 A
—
90
—
ns ^VGS ^{= 10 V}
—
30
—
ns ^{Rg = 25 }
—
0.9
1.5
V
I_F = 5 A, V_GS = 0 ^{Note 4}
— 250
—
ns I_F = 5 A, V_GS = 0
V_DD = 250 V
di_F/dt = 100 A/s
R07DS0050EJ0200 Rev.2.00
Jul 22, 2010
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