R8A66162SP Datasheet, PDF (2/8 Pages) Renesas Technology Corp – 32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH

R8A66162SP
PIN CONFIGURATION ( TOP VIEW )
GND
1
Q1
2
PARALLEL
DATA
OUTPUTS
Q2
3
Q3
4
Q4
5
Q5
6
Q6
7
GND
8
VCC
9
SERIAL DATA INPUT
A
10
OUTPUT ENABLE INPUT OE
11
LATCH ENABLE INPUT
LE
12
DIRECT SET INPUT
SD
13
SHIFT CLOCK INPUT
CK
14
VCC
15
GND
16
SERIAL DATA OUTPUT
SQ32
17
Q27
18
PARALLEL
DATA
OUTPUTS
Q28
19
Q29
20
Q30
21
Q31
22
Q32
23
GND
24
48
Q7
47
Q8
PARALLEL
46
Q9
DATA
45
Q10
OUTPUTS
44
Q11
43
GND
42
Q12
41
Q13
PARALLEL
40
Q14
DATA
39
Q15
OUTPUTS
38
Q16
37
VCC
36
GND
35
Q17
34
Q18
PARALLEL
33
Q19
DATA
32
Q20
OUTPUTS
31
Q21
30
GND
29
Q22
28
Q23
PARALLEL
27
Q24
DATA
26
Q25
OUTPUTS
25
Q26
FUNCTIONAL DESCRIPTION
The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and
maintains high noise margin as well as high output current and high speed required to drive LEDs.
Each shift register bit consists of a flip-flop for shifting and an output latch.
The shift operation takes place when the shift clock input CK changes from low-level to high-level.
The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is
shifted in sequence when a pulse is applied to CK.
If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched.
The parallel data outputs Q₁~Q₃₂ are open-drain outputs.
To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of
the 32nd bit.
If the direct set input SD is turned low-level, Q₁~Q₃₂ and SQ₃₂ are set. Then shift register and latches are set.
If the high-level input is applied to the output enable input OE, Q₁~Q₃₂ are set to the high-impedance state,
but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed.
REJ03F0263-0100 Rev.1.00 Jan.24.2008
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