R1LV1616HBG-I_17 Datasheet, PDF (2/15 Pages) Renesas Technology Corp – 16 M SRAM (1-Mword x 16-bit)

R1LV1616HBG-I Series
Pin Arrangement
48-ball FBGA
1 2 34 5 6
A ^LB# OE# ^{A0 A1 A2} CS2
B ^I/O8 UB# ^{A3 A4 CS1#} I/O0
C ^I/O9 I/O10 ^{A5 A6 I/O1} I/O2
D ^Vss I/O11 ^{A17 A7 I/O3} Vcc
E Vcc I/O12 Vss A16 I/O4 Vss
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 A19 A12 A13 WE# I/O7
H A18 A8 A9 A10 A11 NU
(Top view)
Pin Description
Pin name
Function
A0 to A19
Address input
I/O0 to I/O15
Data input/output
CS1# (CS1)
Chip select 1
CS2
Chip select 2
WE# (WE)
Write enable
OE# (OE)
Output enable
LB# (LB)
Lower byte select
UB# (UB)
Upper byte select
VCC
Power supply
VSS
Ground
NU*¹
Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
Rev.1.01, Feb.23.2017, page 2 of 13