M62384FP Datasheet, PDF (2/8 Pages) Renesas Technology Corp – 8-Bit, 4-Channel, 3 to 5 V D-A Converter (Buffered)

M62384FP
Block Diagram
SDI 11
SCK ¹²
VDD ₁₃
RST ₁₄
Power-on
reset
12-bit shift register
Channel
8
decoder
10 SLD
16 CS1
15 CS0
VSS ⁹
Vref ⁵
VCC 4
8-bit latch
8-bit D-A
8-bit latch
8-bit D-A
8-bit latch
8-bit D-A
8-bit latch
8-bit D-A
1 _GND
2
3
6
7
Ao1
Ao2
Ao3
Ao4
Pin Functions
Pin No.
Symbol
1, 8
GND
2
Ao1
3
Ao2
6
Ao3
7
Ao4
4
Vcc
5
Vref
9
Vss
10
SLD
11
SDI
12
SCK
13
VDD
14
RST
15
CS0
16
CS1
Function
Analog GND: analog circuit GND
(D-A converter lower reference voltage)
D-A converter output pins (ch1 to ch4): full-swing buffer output
Output voltage: Ao (00)h = 0V, Ao (FF)h = 255/256 × VREF
Analog power supply (3 V to 5 V)
Must rise simultaneously with VDD or after VDD rise.
D-A converter upper reference voltage input pin
Digital GND
Serial load signal input pin (Schmitt trigger input: with input hysteresis)
When SLD is high, data is loaded from shift register into 8-bit latch corresponding to
address.
Serial data input pin (TTL input in case of 5 V power supply)
Inputs serial data with a 12-bit data length (MSB-first).
Serial clock signal input pin (Schmitt trigger input: with input hysteresis)
At rising edge, data is read into shift register one bit at a time.
Digital power supply pin (3 V to 5 V)
When power supply rises, D-A output is reset (0 V output: power-on reset).
Forced reset pin (TTL input in case of 5 V power supply)
L: D-A output (AO1 to 4) = Fixed setting of 0 V
H: Reset release (power-on reset operation)
Chip select pins (TTL input in case of 5 V power supply)
Access possible only when chip select data (D11, D10) and pin (CS1, CS0) logic
match.
REJ03F0077-0200 Rev.2.00 Mar 25, 2008
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