M5M5V5636GP-16I Datasheet, PDF (2/18 Pages) Renesas Technology Corp – 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

January 31, 2003 Rev.0.1
Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Mitsubishi's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5V5636GP operates on 3.3V
power/ 2.5V I/O supply or a single 3.3V power supply and are
3.3V CMOS compatible.
FEATURES
• Supported Industrial Temperature Range
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz and 133MHz
• Fast access time: 3.8 ns and 4.2ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
MITSUBISHI LSIs
M5M5V5636GP –16I,13I
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
100pin TQFP
PART NAME TABLE
Part Name
M5M5V5636GP – 16I
M5M5V5636GP – 13I
Access
3.8ns
4.2ns
Cycle
6.0ns
7.5ns
Active Current
(max.)
380mA
350mA
Standby Current
(max.)
30mA
30mA
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Preliminary
M5M5V5636GPI REV.0.1