HD74LS259 Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – 8-bit Addressable Latches

HD74LS259
Pin Arrangement
Latch
Select
A1
B2
C3
Q0 4
Q1 5
Outputs
Q2 6
Q3 7
GND 8
A
B
CLR
C
G
Q0
D
Q1
Q7
Q2
Q6
Q3
Q5
Q4
16 ^VCC
15 Clear
14 Enable
13 Data Input
12 Q7
11 Q6
Outputs
10 Q5
9 Q4
(Top view)
Function Table
Input
CLR
G
H
L
H
H
L
L
L
H
Output of
addressed latch
D
Qio
D
L
Each other output
Qio
Qio
L
L
Function
Addressable latch
Memory
8-line demultiplexer
Clear
Select inputs
Latch addressed
C
B
A
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
Notes: 1. H; high level, L; low level
2. D; the level at the data input
3. O_io; the level of Q_i (i = 0, 1, … 7, as appropriate) before the indicated steady state input conditions were
established.
Rev.2.00, Feb.18.2005, page 2 of 7