HD74HC299 Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – 8-bit Universal Shift/Storage Register (with 3-state outputs)

HD74HC299
Function Table
Inputs
Mode
Function Output
Serial
Clear Select Control Clock
Inputs/Outputs
Outputs
S₁ S₀ G₁† G₂†
S_L S_R A/Q_A B/Q_B C/Q_C D/Q_D E/Q_E F/Q_F G/Q_G H/Q_H Q_A’ Q_H’
Clear L X L L L X X X L L L L L L L L L L
L L X L L X XXL L L L L L L L L L
Hold H
L
L
L
L
X
X
X Q_A0 Q_B0 Q_C0 Q_D0 Q_E0 Q_F0 Q_G0 Q_H0 Q_A0 Q_H0
H XXL L
L
X
X Q_A0 Q_B0 Q_C0 Q_D0 Q_E0 Q_F0 Q_G0 Q_H0 Q_A0 Q_H0
Shift H L H L L
Right H L H L L
X
H
H Q_An Q_Bn Q_Cn Q_Dn Q_En Q_Fn Q_Gn H Q_Gn
X
L
L Q_An Q_Bn Q_Cn Q_Dn Q_En Q_Fn Q_Gn L Q_Gn
Shift H H L L L
Left
H HLLL
H
X Q_Bn Q_Cn Q_Dn Q_En Q_Fn Q_Gn Q_Hn H Q_Bn H
L
X Q_Bn Q_Cn Q_Dn Q_En Q_Fn Q_Gn Q_Hn L Q_Bn L
Load H H H X X
XXa b c d e f g h a h
Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flip-
flop outputs are isolated from the input/output terminals.
2. Q_A0 to Q_H0; the level of Q_A through Q_H, respectively, before the indicated steady-state input conditions were
established.
3. Q_An to Q_Hn; the level of Q_A through Q_H, respectively, before the most-recent transition of the clock.
4. † ; When one or both output controls are high the eight input/output terminals are disabled to the high-
impedance state, however, sequential operation or clearing of the register is not affected.
5. When clear is low, outputs of Q_A’ and Q_H’ are low, in spite of other inputs.
Pin Arrangement
S0 1
Output ^{G1 2}
controls _{G2 3}
G/QC 4
E/QE 5
C/QC 6
A/QA 7
QA 8
Clear 9
GND 10
S0 _S1
G
SL
G/QG QH
E/QE H/QH
C/QC F/QF
A/QA D/QD
QA
B/QB
ClearSR CK
(Top view)
20 VCC
19 S1
18
Shift left
SL
17 QH
16 H/QH
15 F/QF
14 D/QD
13 B/QB
12 Clock
11
Shift right
SR
Rev.2.00 Jan 31, 2006 page 2 of 8