HD74AC283 Datasheet, PDF (2/10 Pages) Hitachi Semiconductor – 4-bit Binary Full Adder with Fast Carry

HD74AC283/HD74ACT283
Logic Symbol
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
Pin Names
A₀ – A₃
B₀ – B₃
C₀
S₀ – S₃
C₄
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
Functional Description
The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C₀). The binary sum
appears on the Sum (S₀ – S₃) and outgoing carry (C₄) outputs. The binary weight of the various inputs and outputs is
indicated by the subscript numbers, representing powers of two.
2⁰ (A₀ + B₀ + C₀) + 2¹ (A₁ + B₁) + 2² (A₂ + B₂) + 2³ (A₃ + B₃) = S₀ + 2S₁ + 4S₂ + 8S₃ + 16C₄
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation. Thus C₀, A₀, B₀ can be arbitrarily assigned to pins 5,
6 and 7 for DIPS. Due to the symmetry of the binary add function, the HD74AC283/HD74ACT283 can be used either
with all inputs and outputs active High (positive logic) or with all inputs and outputs active Low (negative logic). See
Figure a. Note that if C₀ is not used it must be tied Low for active High logic or tied High for active Low logic.
Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for use as inputs
or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an
intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A₃, B₃)
Low makes S₃ dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle
Figure c shows a way of dividing the HD74AC283/HD74ACT283 into a 2-bit and a 1-bit adder. The third stage adder
(A₂, B₂, S₂) is used merely as a means of getting a carry (C₁₀) signal into the fourth stage (via A₂ and B₂) and bringing
out the carry from the second stage on S₂. Note that as long as A₂ and B₂ are the same, whether High or Low, they do
not influence S₂. Similarly, when A₂ and B₂ are the same the carry into the third stage does not influence the carry out
of the third stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.
The outputs S₀, S₁ and S₂ present a binary number equal to the number of inputs I₁ – I₅ that are true. Figure e shows one
method of implementing a 5-input majority gate. When three or more of the inputs I₁ – I₅ are true, the output M₅ is true.
Fig. a Active HIGH varsus Active LOW Interpretation
Logic levels
C₀
A₀
A₁
L
L
H
Active HIGH 0
0
1
Active LOW
1
1
0
Active HIGH: 0 + 10 + 9 = 3 + 16
Active LOW: 1 + 5 + 6 = 12 + 0
A₂
L
0
1
A₃
H
1
0
B₀
H
1
0
B₁
L
0
1
B₂
L
0
1
B₃
H
1
0
S₀
H
1
0
S₁
H
1
0
S₂
L
0
1
S₃
L
0
1
C₄
H
1
0
Rev.2.00, Jul.16.2004, page 2 of 9