HD74AC175 Datasheet, PDF (2/8 Pages) Hitachi Semiconductor – Quad D-Type Flip-Flop

HD74AC175
Logic Symbol
D0
D1
D2
D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
Pin Names
D₀ to D₃
CP
MR
Q₀ to Q₃
Q₀ to Q ₃
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High
clock (CP) transition, causing individual Q and Q outputs to follow. A Low input on the Master Reset (MR) will force
all Q outputs Low and Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general
logic applications where a common Master Reset and Clock are acceptable.
Truth Table
Inputs
Outputs
@ t_n, MR = H
@ t_n+1
Dn
Qn
Qn
L
L
H
H
H
L
H : High Voltage Level
L : Low Voltage Level
t_n : Bit Time before Clock Pulse
t_{n + 1} : Bit Time after Clock Pulse
Rev.2.00, Jul.16.2004, page 2 of 7