HD74AC166 Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – 8-bit Shift Register

HD74AC166/HD74ACT166
Logic Symbol
15 2 3 4 5 10 11 12 14
PE P0 P1 P2 P3 P4 P5 P6 P7
1
DS
7
6
1
2
CP
MR
Q7
9
13
VCC=Pin16
GND=Pin8
Pin Names
CP₁, CP₂
D_S
PE
P₀ to P₇
MR
Q₇
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Parallel Enable Input (Active Low)
Parallel Data Inputs
Asynchronous Master Reset Input (Active Low)
Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock
input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should
attain the High state while the other clock is still in the High state following the previous operation. When the Parallel
Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P₀ to P₇) inputs on the next rising edge
of the clock. When PE is High, information is shifted from the Serial Data (D_S) input to Q₀ and all data in the register is
shifted one bit position (i.e., Q₀ → Q₁, Q₁ → Q₂, etc.) on the rising edge of the clock.
Truth Table
Inputs
MR
PE
L
X
CP₂
X
CP₁
X
H
X
L
L
H
L
L
H
H
L
H
H
L
H
X
H
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Clock Transition
D_S
X
X
X
H
L
X
Parallel
P₀ to P₇
X
L
X
Q_A0
a ··· h
a
X
H
X
L
X
Q_A0
Internal Outputs
Q₀
Q₆
L
Q_B0
b
Q_An
Q_An
Q_B0
Output
Q₇
L
Q_H0
h
Q_Gn
Q_Gn
Q_H0
Rev.2.00, Jul.16.2004, page 2 of 8