TAS5102 Datasheet, PDF (19/25 Pages) Texas Instruments – 20-W/15-W STEREO DIGITAL AMPLIFIER POWER STAGE

TAS5102
TAS5103
www.ti.com .............................................................................................................................................................. SLLS801A – JUNE 2008 – REVISED JUNE 2008
condition has been removed. For highest possible
reliability, recovering from an overcurrent fault
requires external reset of the device (see the Device
Reset section of this data sheet) no sooner than 300
ms after the shutdown.
Use of TAS5102/3 in High-Modulation-Index
Capable Systems
This device requires at least 50 ns of low time on the
output per 384-kHz PWM frame rate in order to keep
the bootstrap capacitors charged. As an example, if
the modulation index is set to 99.2% in the TAS5086,
this setting allows PWM pulse durations down to 20
ns. This signal, which does not meet the 50-ns
requirement, is sent to the PWM_X pin, and this
low-state pulse time does not allow the bootstrap
capacitor to stay charged. In this situation, the low
voltage across the bootstrap capacitor can cause the
bootstrap UVP circuitry to activate and shutdown the
device. The TAS5102/3 device requires limiting the
TAS5086 modulation index to 96.1% to keep the
bootstrap capacitor charged under all signals and
loads.
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5508 or TAS5086, with the
modulation index set at 96.1% to interface with
TAS5102/3. This is done by writing 0x04 to the
Modulation Limit Register (0x10) in the TAS5086 or
0x04 to the Modulation Limit Register (0x16) in the
TAS5508.
Overcurrent (OC) Protection With Current
Limiting
The device has independent, fast-reacting current
detectors on all high-side and low-side power-stage
FETs. The detector outputs are closely monitored by
two protection systems. The first protection system
controls the power stage in order to prevent the
output current further increasing, i.e., it performs a
cycle-by-cycle current-limiting function, rather than
prematurely shutting down during combinations of
high-level music transients and extreme speaker load
impedance drops. If the high-current condition
situation persists, i.e., the power stage is being
overloaded, a second protection system triggers a
latching shutdown, resulting in the power stage being
set in the high-impedance (Hi-Z) state. Current
limiting and overcurrent protection are not
independent for half-bridges A and B and,
respectively, C and D. That is, if the bridge-tied load
between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D are shut down.
The overcurrent protection threshold is set by a
resistor to ground from the OC_ADJ pin. A value of
22kΩ will result in an overcurrent threshold of 4.5 A.
Overtemperature Protection
The
TAS5102/3
has
a
two-level
temperature-protection system that asserts an
active-high warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. OTE is latched in this case. To clear
the OTE latch, RESET must be asserted. Thereafter,
the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5102/3 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_XY and VREG supply voltages reach 5.7 V
(typical) and 2.7 V, respectively. Although GVDD_XY
and VREG are independently monitored, a supply
voltage drop below the UVP threshold on VREG or
either GVDD_XY pin results in all half-bridge outputs
immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device
automatically resumes operation when all supply
voltages have increased above the UVP threshold.
DEVICE RESET
One reset pin is provided for control of half-bridges
A/B/C/D. When RESET is asserted low, all four
power-stage FETs in half-bridges A, B, C, and D are
forced into a high-impedance (Hi-Z) state. Thus, the
reset pin is well suited for hard-muting the power
stage if needed.
In BTL modes, to accommodate bootstrap charging
prior to switching start, asserting the reset input low
enables weak pulldown of the half-bridge outputs. In
the SE mode, the weak pulldowns are not enabled,
and it is therefore recommended to ensure bootstrap
capacitor charging by providing a low pulse on the
PWM inputs when reset is asserted high.
Asserting the reset input low removes any fault
information to be signaled on the FAULT output, i.e.,
FAULT is forced high.
A rising-edge transition on the reset input allows the
device to resume operation after an overcurrent fault.
Copyright © 2008, Texas Instruments Incorporated
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