RMQC4A1836DGBA_15 Datasheet, PDF (19/30 Pages) Renesas Technology Corp – 18-Mbit DDR™ II SRAM 2-word Burst

RMQC4A1836DGBA, RMQC4A1818DGBA
Datasheet
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This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
V_DD and V_DDQ slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time
begins once V_DD , V_DDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
Transitions are measured ±100 mV from steady-state voltage.
These parameters are only guaranteed by design and are not tested in production.
Remarks:
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Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
Control input signals may not be operated with pulse widths less than t_KHKL (min).
If C, /C are tied high, K, /K become the references for C, /C timing parameters.
V_DDQ is +1.5 V DC. V_REF is +0.75 V DC.
Control signals are /R and /W.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
In the case of running frequency between 250MHz and 300MHz, all the AC/DC parameters follow
300MHz.
In the case of running frequency between 300MHz and 333MHz, all the AC/DC parameters follow
333MHz.
R10DS0248EJ0100 Rev.1.00
Jan. 13, 2015
Page 19 of 29