U19858EJ1V0PM00_15 Datasheet, PDF (18/25 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCONTROLLER

μPD78F8056, 78F8057, 78F8058
(3) DMA CONTROLLER
Data can be automatically transferred between SFRs of the peripheral hardware supporting DMA and internal RAM
without via CPU by DMA triggers.
DMA triggers are selected by setting IFCn3 to IFCn0, bit 3 to 0 of DMA mode control register (DMCn). The following
DMA triggers are selectable.
IFCn3 IFCn2 IFCn1 IFCn0
Selection of DMA start source
Trigger signal
Trigger contents
0
0
0
0
−
Disable DMA transfer by interrupt.
(Only software trigger is enabled.)
0
0
1
0 INTTM00
End of timer array unit 0 channel 0 count or
capture
0
0
1
1 INTTM01
End of timer array unit 0 channel 1 count or
capture
0
1
0
0 INTTM04
End of timer array unit 0 channel 4 count or
capture
0
1
0
1 INTTM05
End of timer array unit 0 channel 5 count or
capture
0
1
1
0 INTCSI00
CSI00 transmission transfer end
1
0
0
0 INTST1/INTCSI10/INTIIC10 UART1 transmission transfer end or
CSI10 transmission transfer end or IIC10
transmission transfer end
1
0
0
1 INTSR1
UART1 reception end interrupt
1
0
1
0 INTST3
UART3 transmission transfer end interrupt
1
0
1
1 INTSR3
UART3 reception end interrupt
Other than above
Setting prohibited
Remark n: DMA channel number (n=0, 1)
Please refer to user manual of 78K0R/KF3-L (U19459E) for the details.
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Preliminary Product Information U19858EJ1V0PM