R32C121 Datasheet, PDF (18/113 Pages) Renesas Technology Corp – RENESAS MCU

Under development
R32C/121 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
3. Memory
3. Memory
Figure 3.1 shows a memory mapping of the R32C/121 Group.
The R32C/121 Group provides 4-Gbyte address space from 00000000h to FFFFFFFFh.
The internal ROM is allocated from address FFFFFFFFh down. For example, a 512-Kbyte internal ROM is
addressed from FFF80000h to FFFFFFFFh.
The fixed interrupt vectors are allocated from address FFFFFFDCh to FFFFFFFFh in which the starting
address of each interrupt handler is stored.
The internal RAM is allocated from address 00000400h up. For example, a 32-Kbyte internal RAM is
addressed from 00000400h to 000083FFh. Besides being used for data storage, the internal RAM functions
as stack(s) for a subroutine and/or an interrupt handler.
Special Function Registers (SFRs), consisting of control registers for peripheral functions, are allocated
from address 00000000h to 000003FFh and from 00040000h to 0004FFFFh. Any blank spaces within the
SFRs are reserved. No access is allowed.
Internal RAM
Capacity XXXXXXXXh
12 Kbytes 00003400h
20 Kbytes 00005400h
24 Kbytes 00006400h
32 Kbytes 00008400h
Internal ROM
Capacity YYYYYYYYh
128 Kbytes FFFE0000h
256 Kbytes FFFC0000h
384 Kbytes FFFA0000h
512 Kbytes FFF80000h
00000000h
00000400h
XXXXXXXXh
SFR1
Internal RAM
Reserved
00040000h
00050000h
00060000h
00062000h
SFR2
Reserved
Internal ROM
(Data space) ⁽¹⁾
Reserved
YYYYYYYYh
FFFFFFFFh
Internal ROM
FFFFFFDCh
FFFFFFFFh
Undefined instruction
Overflow
BRK instruction
Reserved
Reserved
Watchdog timer ⁽²⁾
Reserved
NMI
Reset
Notes:
1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.
2. The watchdog timer interrupt shares the vector table with the oscillation stop detection interrupt and low-
voltage detection interrupt.
Figure 3.1 Memory Mapping
REJ03B0237-0050 Rev.0.50 Jul 31, 2008
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