R1QPA4436RBG_15 Datasheet, PDF (18/31 Pages) Renesas Technology Corp – 144-Mbit QDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT

R1QPA4436RBG,R1QPA4418RBG
Output load conditions
1.8V±0.1V 1.5V
V_DDQ / 2
= 0.75V
V_DD
V_DDQ
V_REF
SRAM
V_SS
Q
250Ω
ZQ
Z₀ = 50Ω
Datasheet
V_DDQ / 2
= 0.75V
50Ω
AC Operating Conditions
Parameter
Symbol
Min
Typ
Input high voltage V_{IH (AC)} V_REF + 0.2
-
Input low voltage
V_{IL (AC)}
-
-
Max
-
V_REF – 0.2
Unit
V
V
Notes
1,2,3,4
1,2,3,4
Notes:
1.
2.
3.
4.
All voltages referenced to V_SS (GND). During normal operation, V_DDQ must not exceed V_DD.
These conditions are for AC functions only, not for AC parameter test.
Overshoot: V_{IH (AC)} ≤ V_DDQ + 0.5 V for t ≤ t_KHKH/2
Undershoot: V_{IL (AC)} ≥ −0.5 V for t ≤ t_KHKH/2
Control input signals may not have pulse widths less than t_KHKL (min) or operate at cycle rates less than t_KHKH
(min).
To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, V_{IL (AC)} or V_{IH (AC)}.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, V_{IL (DC)} or V_{IH (DC)}.
R10DS0147EJ0200 Rev.2.00
Aug 01, 2014
Page 18 of 30