M37906M4C-XXXFP Datasheet, PDF (18/102 Pages) Renesas Technology Corp – 16-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
PRELIMINARY _{NSootimcee: pTahriasmisentroict} ^{alimfinitsalasrpeescuifbicjeactitotno. change.}
M37906M4C-XXXFP,
M37906M4H-XXXSP,
M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is trans-
ferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ de-
pending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory or internal peripheral devices, at first, the CPU informs the
BIU’s data address register of the address where the data has been
located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
(3) Data write operation
When executing an instruction for writing data into the internal
memory or internal peripheral devices, at first, the CPU informs the
BIU’s data address register of the address where the data has been
located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory or internal peripheral devices.
This operation is called “bus cycle”. The bus cycle is affected by the
lengh of data to be transferred (byte, word, or double-word) at data
access.
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
Even address
4-byte boundary
8-byte boundary
AD2 (A2)
X
X
0
AD1 (A1)
X
0
0
AD0 (A0)
0
0
0
X: 0 or 1
Figures 7 and 8 show the bus cycle waveform examples for instruc-
tion prefetch and data access.
Access to internal area
When branched or at instruction
prefetch
φBIU
Internal address bus _Address
Internal code bus
CB0 to CB31
Code
Fig. 7 Bus cycle waveform example for instruction prefetch
17