H83672 Datasheet, PDF (172/332 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

Section 11 Timer W
Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0200
H'0000
GRD H'0200
H'0450
H'0450
H'0520
H'0520
Time
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 11.11 Buffer Operation Example (Output Compare)
Figures 11.12 and 11.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
Rev.4.00 Nov. 02, 2005 Page 148 of 304
REJ09B0143-0400